We have following urgent need with our client
Title: RTL Design Engineer / Physical Design Engineer
Duration: 6 to 12+ Months
Location – Hillsboro, OR
Scratch RTL design for any/some of the following:
- ASIC front-end development.
- Logic design, RTL coding, verification, synthesis, and timing closure.
- Synopsys DC/PrimeTime or similar tools.
- Scripting/programming in Tcl, Perl/Csh.
- Memory subsystem with multiple banking multiple reports, crossbar connection to computing elements
- 3-D, 4-D descriptor based DMA controller with out of order responses
- the DSP functionality knowledge, integer/float multiply – accumulate, and nonlinear functions such as sigmoid, relu, tanh, quantization, reduction
- Unix/Linux shell programming, Perl, Java, Makefile, XML.
- Tools: UVM, System Verilog, Perl, all Cadence front/back end tools
* 3+ years of industry experience in 1 or more of the following technical disciplines:
• SoC Design (ASIC integration, Peripherals, Bus Design, DC/PC, LINT, PTSI)
• RTL Design (Functional/Structural, Partitioning, Simulation, Regression, Modelsim, VCS, Design Compiler, Primetime, Microprocessor Architecture, Memory Coherency)