Title: DFT Engineer 

Location - Menlo Park, CA

Duration: 1+ years
 

Responsibilities

• Work with the Silicon teams to establish DFT requirements and the DFT Architecture needed to achieve product quality goals
• Develop and implement DFT features and methodologies optimized for PPAS and verified
• Improve execution efficiency and QOR through flow automation and dashboard checks
• Manage schedules and support internal and external cross-functional/cross-organizational engineering efforts
• Support silicon bring-up, debug and ramp to production
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Minimum Qualification

• 5+ years Design for Test experience on complex SoC’s including architecture specification, Implementation, test pattern development and verification
• Master’s degree in Computer Engineering, Electrical Engineering or similar Engineering field or BS and 5+ years Industry experience
• Knowledge about industry standards and practices in DFT, ATPG, JTAG, Memory BIST, and trade-offs between test quality and product impact (power, performance, area, schedule)
• Experience with yield enhancement methods such as memory repair and in-system operation
• Proficient with commercially available DFT, design and verification tools
• Experience in debugging DFT patterns in simulation and on ATE

 

Preferred Qualification

• Experience with running synthesis and developing STA constraints for DFT operation modes
• Experience with running and debugging SDF back-annotated simulations
• Experience with power-aware DFT, power delivery networks and their unique interaction with DFT architectures and implementations
• Experience with Analog DFT and Analog Mixed Signal IP test methods and integration
• Proficiency with programming and scripting languages such as Perl/TCL