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Design Verification Engineer

Santaclara, CA
We have the following urgent requirement with our client:
Title:  Design Verification Engineer
Location: Santa Clara, CA.
Duration:  6 Months

Desired Skills & Experience:
·       Experience level 6+ years preferred
·      Expertise in System Verilog
·       Strong in SV & OOPS
·       Experience in OVM is needed
*      Education: B.Tech/B.E.


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