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Design Verification Engineer

Santa Clara, CA
We have the following urgent requirement with our client:
 
Title:  Design Verification Engineers
Opening: Multiple

Location: Santa Clara, CA
Duration:  6 to 12+ months
Compensation:  DOE

Details
• Requires strong experience with development of UVM, OVM, VMM and/or Verilog, SystemVerilog test benches for full chip testbench and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test full chip FPGA fabric and SoCs.
• Requires strong understanding of state of the art of verification techniques, including assertion and metric-driven verification.
• Verification experience AXI, NoC, HBM, DDR4, PCIe verification is a plus.
• Verification experience in full chip verification is a plus.
• Strong understanding of different phases of ASIC and/or full custom chip development is required.
• Experience in modeling SystemC and using SystemC based models in verification is a plus.
• Experience with FPGA programming and software is a plus.
• Verification experience in  PCIe, Processors, Graphics is a plus.
• Experience with formal property checking tools such as Cadence (IEV), Jasper, and Synopsys (Magellan) is a plus.
• Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
• Some DFX/DFT and UPF/power-aware-simulation experience is a plus

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