We are urgently looking for Analog Engineer
for our Direct client requirement
TITLE: Analog Engineer
LOCATION: Santa Clara, CA.
DURATION: 6 to 12+ Months
- Architect and Create verification environments using System Verilog and Universal verification methodology-UVM for ASlCs, and SoCs with embedded CPUs and analog mixed-signal Interfaces.
- Integrate Matlab and C model into SoC and Block level verification Environments.
- Develop test plans and coverage metrics from specifications and writing block and chip-level tests.
- Create PERL/Python scripts to automate creating verification environments, tests generation and debugging.
- Failure analysis of Register Transfer Level and Gate simulations and resolve them by working with design engineers.
- Create low power testcases using UPF or CPF to verify the desired power intent of the SoC.
- Work with architects to determine the use-case scenarios to simulate.
- Write diagnostics for validation of Field Programmable Gate Array prototype and Application-Specific Integrated Circuit.
- Participate in silicon bring-up for features owned and replicate silicon bugs in simulation environment and validating fixes for software workarounds.
- Convert verification tests to test patterns and assisting Test Engineers on Automated Test Equipment (ATE) vector bring up.
- Evaluate latest verification methodologies and developing scripts to automate verification flows.
- Responding to customer requests as they occur and assisting in the development of embedded firmware.