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Analog Engineer

Santa Clara, CA
We are urgently looking for Analog Engineer for our Direct client requirement

TITLE: Analog Engineer
LOCATION: Santa Clara, CA.
DURATION: 6 to 12+ Months

  1. Architect and Create verification environments using System Verilog and Universal verification methodology-UVM for ASlCs, and SoCs with embedded CPUs and analog mixed-signal Interfaces.
  2. Integrate Matlab and C model into SoC and Block level verification Environments.
  3. Develop test plans and coverage metrics from specifications and writing block and chip-level tests.
  4. Create PERL/Python scripts to automate creating verification environments, tests generation and debugging.
  5. Failure analysis of Register Transfer Level and Gate simulations and resolve them by working with design engineers.
  6. Create low power testcases using UPF or CPF to verify the desired power intent of the SoC.
  7. Work with architects to determine the use-case scenarios to simulate.
  8. Write diagnostics for validation of Field Programmable Gate Array prototype and Application-Specific Integrated Circuit.
  9. Participate in silicon bring-up for features owned and replicate silicon bugs in simulation environment and validating fixes for software workarounds.
  10. Convert verification tests to test patterns and assisting Test Engineers on Automated Test Equipment (ATE) vector bring up.
  11. Evaluate latest verification methodologies and developing scripts to automate verification flows.
  12. Responding to customer requests as they occur and assisting in the development of embedded firmware.

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