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Design Verification Engineer

Toronto, Canada

We are urgently looking for Design Verification Engineer for our Direct client.

TITLE:  Design Verification Engineer 
LOCATION: Toronto, Canada.

Job Responsibility
  1. Knowledge of Code coverage using features in existing simulators or stand-alone tools like Surecov, HDL score etc.
  2. Working on full chip verification and OVM/UVM Methodology, System Verilog is a must with 3+years of recent work experience, worked on passing test cases, test benches, Building environment.
  3. Knowledge of Functional coverage using HVL language features or assertions a plus.
  4. Should be ARM based SoC verification only. No need to mention tools.
  5. Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc.
Desired Skills & Experience:
  1. Experience level 4 to 7 years.
  2. Strong domain knowledge on one or more - PCIe,USB, Ethernet, ARM, AHB/AXI, AMBA, Networking, CPU, ARM, Graphics (DDR, PCIE, USB)
  3. Should have worked on SOC verification on at least one project with constrained random methodology (OVM/UVM).
  4. Good in concepts Code coverage and functional coverage.
  5. Expertise in Verilog and / or VHDL is desired.
  6. Strong in SV & OOPS
  7. IP or SoC verification
  8. Functional + code coverage
  9. ARM based SoC verification
  10. Capable of developing C tests
  11. Working knowledge – SV/METH
  12. Code coverage
Education: B.Tech/B.E., in Electronics/Telecommunication, Electrical) OR (PG - M.Tech/M.E, in (Electrical, Electronics/Telecommunication)

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