We are urgently looking for Design Verification Engineer
for our Direct client requirement
TITLE: Design Verification Engineer
LOCATION: Santa Clara, CA.
DURATION: 6+ Months
- Clear case version control
- Inway pre-silicon verification flow
- ANGEL scripting (C/UVM)
- System Verilog
- Verilog AMS
- Python and PERL scripting
- Debug and re run regression test suite
- SPI VIP addition for control Path
- JESD204 addition for
control data Path (typo)
- PHY addition for data Path
- Gate level simulation
- Mixed-signal simulation (analog behavioral model based)
- Power-aware simulation (UPF based)
- Regression list about 2000 testcases.
- Team needs to go through the HAS and collect all required testcases
- All the test cases going to be ported to SPI for control path with synopsys SPI UVM VIP and RTL
- All RX/TX datapath testcases need to be sent new PHY (Synopsys IP) and JESD (Comcore IP).