We are urgently looking for RTL Design Engineer (Digital Module Design)
for our Direct client requirement
TITLE: RTL Design Engineer
LOCATION: Santaclara, CA.
DURATION: 6+ Months
We have a challenging Turnkey project for developing a complex IP sub-system, where we will be executing the entire RTL-2-GDSII flow involving many cutting edge IPs.
We are responsible for IP/RTL integration and configuration, perform SoC level verification, validation of all IPs and implement the physical design of whole sub-system for a successful tape-out.
So we need RTL/Design experienced team of Engineers with below qualification and roles/responsibilities
Minimum qualification for this position are as follows:
Roles & Responsibilities
- Hands-on expertise in writing System Verilog and VHDL
- Experience in Digital module design and micro-architecture
- Experienced at modeling complex state machines, datapaths and bus protocols/high speed (bandwidth) interfaces such as PCIe, USB, HBM, DDRx
- Experience in RTL simulation, synthesis, Linting, CDC checks, STA, DFT, quality metrics
- Qualification and selection of commercial IPs for integration in SoC, and Hands on in SoC level RTL integration
- Hands-on in Perl/Unix scripting, Excellent analytical, and problem solving skills
- Be motivated to continuously develop skills and accept a variety of responsibilities as part of contributing to the project's success
- 10+ years’ industry experience, Master’s degree or equivalent in EE or Computer Engineering (CE)
- Perform detailed block design from system requirements and evolving specifications, and developing timing constraints
- Perform RTL coding, Lint checks, CDC checks, SDC creation, equivalency checking, STA result review, RTL/gate level simulations debugging
- Working closely with synthesis, STA, PD and DFT teams to meet all functional requirements, performance, power and area goals
- Technical interaction with customers and support team.