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Physical Verification EngineerPalo Alto, CA
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TITLE: physical verification Engineer
LOCATION: Palo, Alto , CA.
DURATION: 6 to 12+ Months
Physical Verification with TSMC 7nm
- Hands-on experience in physical verification – DRC, LVS, ERC, ANT running and debugging in 7nm.
- Excellent understanding of the 7nm process technology and DRC rule interpretation.
- Expertise in LVS debugging – short isolation
- Experience with Cadence PVS tool is a plus (but not required).
- Need to work on-site (Palo Alto)