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Physical Verification Engineer

Palo Alto, CA
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TITLE: physical verification Engineer 

LOCATION: Palo, Alto , CA.
DURATION: 6 to 12+ Months

Physical Verification with TSMC 7nm
  1. Hands-on experience in physical verification – DRC, LVS, ERC, ANT running and debugging in 7nm.
  2. Excellent understanding of the 7nm process technology and DRC rule interpretation.
  3. Expertise in LVS debugging – short isolation
  4. Experience with Cadence PVS tool is a plus (but not required).
  5. Need to work on-site (Palo Alto)

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