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Hello,
One of our direct client is urgently looking for Digital Design/RTL/Microarchitecture @ Menlo Park, CA.
Role - Digital Design/RTL/Microarchitecture
Location - Menlo Park, CA
Minimum Qualifications
One of our direct client is urgently looking for Digital Design/RTL/Microarchitecture @ Menlo Park, CA.
Role - Digital Design/RTL/Microarchitecture
Location - Menlo Park, CA
Minimum Qualifications
- BSEE/MSEE/BSCompE/MSCompE with at least 5 years of Verilog/SystemVerilog RTL experience.
- Experience with AMBA / AXI busses
- Conversion of algorithms from a C/C++ reference model to RTL
- Microarchitectural breakdown of algorithms into hardware implementations
- Debugging and improving the performance of algorithmic pipelines
- Lint and CDC experience using Synopsys Spyglass
- Familiarity with Python3/Bash/Tcl scripting is a must
- Experience with fixed-point arithmetic
- Preferred Qualifications
- BSEE/MSEE/BSCompE/MSCompE with at least 10 years of Verilog/SystemVerilog RTL experience
- Experience with video processing or graphics pipelines is a plus
- Experience with back-end implementation flows is a plus
- Experience with high-level synthesis - Mentor Catapult, Vivado HLS - is a plus
- Experienced with a full ASIC/SOC tape out from beginning to end
- Experience with floating-point arithmetic in addition to fixed-point arithmetic