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Design Verification Engineer

Location: San Jose, CA
Job # 9720248
Date Posted : 08-04-2017

We have the following urgent requirement with our direct client:
Title:  Design Verification Engineer 
Location: San Jose, CA
Duration:  6+ months
Compensation:  DOE

Responsibilities Include:
Learn the architecture and micro architecture by studying specifications and direct interaction with architects and logic designers of the GPU memory subsystem.
Develop test plans, test benches and tests, creating sequencers, drivers, checkers, and monitors in a UVM environment.
Enhance test benches and tests to achieve coverage goals.
Apply formal methods to supplement stimulus based verification.
Create and support test environments for different design hierarchy levels.
Support unit and super-unit debug on simulation and emulation platforms.
Technically direct and mentor the GPU memory system verification team.
Experience Requirements:
Experienced with verification methodology such UVM/VMM/OVM. UVM is preferred.
Successfully verified a significant component of a memory hierarchy, e.g. a level2 cache unit.
Developed test plans of complex systems containing multiple state machines and protocol rules.
Composed functional coverage assertions, preferably using system Verilog.

The qualified candidate will possess the following:
BSEE, preferably MSEE or PhD.
At least 5 years of industry experience, 3 of which in a design verification role.
Proficient in System Verilog, C++, Python/Perl.
Excellent verbal and written communication
Specific skill set for memory and l2 cache will be added advantage skills
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