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Design Verification Engineer

Location: Portland, OR
Job # 9475136
Date Posted : 06-15-2017

We have the following urgent requirement with our client:
 
Title:  Design Verification Engineer
Location: Portland, OR
Duration:  9+ months
Compensation:  DOE

Job Responsibility
·       Knowledge of Code coverage using features in existing simulators or stand-alone tools like Surecov, HDL score etc.
·       Working on full chip verification and OVM/UVM Methodology, System Verilog
·       Knowledge of Functional coverage using HVL language features or assertions a plus.
·       Proficiency in one scripting language like Perl, C++, Python, Unix Make, Unix Shell Scripts etc.

Desired Skills & Experience:
·       Experience level 8+ years preferred
·      Strong domain knowledge on one or more - PCIe,USB, Ethernet, ARM, AHB/AXI, AMBA, Networking, CPU, ARM, Graphics (DDR, PCIE, USB)
·       Should have worked on SOC verification on at least one project with constrained random methodology (OVM/UVM).
·       Good in concepts Code coverage and functional coverage.
·       Expertise in Verilog and / or VHDL is desired.
·       Strong in SV & OOPS
·       IP/SoC verification
·       Functional + code coverage

Education: B.Tech/B.E.
 
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