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Design Verification Engineer (UVM / Verilog / C/C++ / BFM Modeling)

Location: Irvine, CA
Job # 11477534
Date Posted : 10-11-2018
We have following urgent role with our  DIRECT client

Title: Design Verification Engineer (UVM / Verilog / C/C++ / BFM Modeling)
DURATION: 6+ months 
Compensation: Competitive ( DOE )

Job Description:

The basic requirements should include:
  1. 5-10 years of experience
  2. Strong experience in UVM
  3. Hands on experience in System Verilog.
  4. Good knowledge of System C/C++
  5. Experience on BFM modeling

Employee Referral Program:

We are hiring !
The Employee referral bonus is $500 per referral after the new full-time employee successfully completes 90 days.
The referral bonus for hourly contractor is $250 after the completion of 90 days.
However, managers who have hiring/team building as part of regular management duties are not eligible in the program.

Please send in resumes to Redolent, Inc., 4620 Fortran Drive, Suite 201, San Jose, CA 95134

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