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Design Verification Engineer - JTAG

Location: Hillsboro, OR
Job # 11417948
Date Posted : 09-26-2018
We have following urgent role with our  DIRECT client

Title: Design Verification Engineer - JTAG
LOCATION: Hillsboro, OR 
DURATION: 6+ months 
Compensation: Competitive ( DOE )

Job Description:

Position Summary:

  • PCI Express(PCIe)  is a protocol for transferring data. 
  • It has a controller and a PHY.
  • PHY has 2 parts a digital part and an analog part. 
  • JTAG experience in verification is dresired
  • We want people who has done verification (mostly UVM) on the controller and the digital part of the PHY.
  •  BFM stand for BUS Functional Module.  It is synonymous to Verification IP or VIP.
  • look for keywords BFM, VIP, UVM and PCIe. 

Employee Referral Program:

We are hiring !
The Employee referral bonus is $500 per referral after the new full-time employee successfully completes 90 days.
The referral bonus for hourly contractor is $250 after the completion of 90 days.
However, managers who have hiring/team building as part of regular management duties are not eligible in the program.

Please send in resumes to Redolent, Inc., 4620 Fortran Drive, Suite 201, San Jose, CA 95134

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