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RTL Design Engineer

Location: Santa Clara, CA
Job # 10915939
Date Posted : 04-30-2018
We have following urgent need with our client

Title: RTL Design Engineer
Openings: Multiple
Duration: 6 to 12+ Months
Location – Santa Clara, CA
Rate: Market

Scratch RTL design for any/some of the following:
  • ASIC frontend development.
  • Logic design, RTL coding, verification, synthesis, and timing closure.
  • Synopsys DC/PrimeTime or similar tools.
  •  Scripting/programming in C/C++, Tcl, Perl/Csh.
  • Memory subsystem with multiple banking multiple reports, crossbar connection to computing elements
  • 3-D, 4-D descriptor based DMA controller with out of order responses
  • the DSP functionality knowledge, integer/float multiply – accumulate, and nonlinear functions such as sigmoid, relu, tanh, quantization, reduction
  • Unix/Linux shell programming, Perl, Java, Makefile, XML.
  • Tools: UVM, System Verilog, Perl, all Cadence front/back end tools
Preferred Qualificaitons
3+ years of industry experience in 1 or more of the following technical disciplines:
•  SoC Design (ASIC integration, Peripherals, Bus Design, DC/PC, LINT, PTSI)
•  RTL Design (Functional/Structural, Partitioning, Simulation, Regression, Modelsim, VCS, Design Compiler, Primetime, Microprocessor Architecture, Memory Coherency)
•  Low Power Design (clock gating, power gating, power grids, Power Artist, UPF, CPF)

Employee Referral Program:

We are hiring !
The Employee referral bonus is $500 per referral after the new full-time employee successfully completes 90 days.
The referral bonus for hourly contractor is $250 after the completion of 90 days.
However, managers who have hiring/team building as part of regular management duties are not eligible in the program.

Please send in resumes to Redolent, Inc., 4620 Fortran Drive, Suite 201, San Jose, CA 95134

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