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ASIC Physical Design / STA Engineer

Location: Austin, TX
Job # 10765111
Date Posted : 03-29-2018
We have the following urgent requirement with our client:
 
Title:  ASIC Physical Design / STA Engineer
Location: Austin, TX
Duration: 8+ Months
Compensation: DOE
 
Job Responsibility 
  • Responsibilities includes all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, IP integration, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out. Should be able to interface with Front End Design team to resolve Design Issues
  • Mentoring new team member
Desired Skills:
  • Chip Level Static Timing Analysis, Constraints analysis and Timing closure activities including ECO implementation to fix timing issues on post route database
  • Strong STA skills including PrimeTime/PrimeTime SI timing analysis, Perl/tcl programming experience is a plus
 
EXPERIENCE AND EDUCATION:
  • SoC Architecture; knowledge and hand-on experience from industry ASIC design flow including RTL coding, debugging/verification, and supporting synthesis and timing closure. Working knowledge of ARM cores and other I/O standard interfaces.
  • An ideal candidate would also exhibit: Strong communication and documentation skills, Good organizational, time management and multitasking skills, Strong initiative and discipline to follow-through, Technical leadership
 
 


Employee Referral Program:

We are hiring !
The Employee referral bonus is $500 per referral after the new full-time employee successfully completes 90 days.
The referral bonus for hourly contractor is $250 after the completion of 90 days.
However, managers who have hiring/team building as part of regular management duties are not eligible in the program.

Please send in resumes to Redolent, Inc., 4620 Fortran Drive, Suite 201, San Jose, CA 95134


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