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RTL Design Engineers

Location: Santa Clara, CA
Job # 10432993
Date Posted : 02-15-2018
We have the following urgent requirement with our client:

Title: RTL Design Engineers
Location- Santa Clara, CA
Duration: 8+ Months
Rate: Market

Job Details:
  • 8+ years of industry experience in the following areas:
  • ASIC frontend development.
  • Logic design, RTL coding, verification, synthesis, and timing closure.
  • Hardware description languages (Verilog, System Verilog and VHDL).
  • AMBA bus standards such as AXI, AHB, and ACE
  • Synopsys DC/PrimeTime or similar tools.
  • Scripting/programming in C/C++, Tcl, Perl/Csh.
 Preferred Qualifications:
  • 5+ years of industry experience in 1 or more of the following technical disciplines:
  • SoC Design (ASIC integration, Peripherals, Bus Design, DC/PC, LINT, PTSI)
  • RTL Design (Functional/Structural, Partitioning, Simulation, Regression, Modelsim, VCS, Design Compiler, Primetime, Microprocessor Architecture, Memory Coherency)
  • Low Power Design (clock gating, power gating, power grids, Power Artist, UPF, CPF)
  • High-Speed DDR Controller (Memory Controller, CPU, SRAM & L3 Cache, x86 or ARM CPU/bus architecture)
  • Audio Codec ASIC Hardware (Audio DSP Implementation, Audio Algorithm, Low-Power Voice/Audio Activation, Noise Cancellation)
  • Graphic ASIC Hardware (GPU or CPU cores, DX9/10/11 level graphics HW development)
  • Multimedia/Camera Imaging/Video (Image processing algorithms, ASIC Design, RTL Coding, JPEG, C/C++/SystemC, Modelsim, Synopsys DC, LEC, Spyglass)
  • Physical Layer Design (PHY, USB, HDMI, DDR, MIPI)
  • SerDes Application (PHY Layer Protocol, SerDes PHY, ASIC EDA Models, Cadence Schematics)
  • Digital Design for Mixed Signal ASICs (PLL, Phase-Lock-Loop, LNA, OpAmp, ADC-DAC)
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