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Design Verification Engineer

Location: San Jose, CA
Job # 10151155
Date Posted : 11-14-2017
We have the following urgent requirement with our client:

Title:  Design Verification Engineer
Location:  San Jose-CA
Duration:  6 Months
Compensation: DOE

Required Skills:
  • At least 5 years of industry experience,
  • 3 years experience design verification role.​
  • Proficient in System Verilog, C++, Python/Perl.​
Responsibilities Include:
  • Learn the architecture and micro architecture by studying specifications and direct interaction with architects and logic designers of the GPU memory subsystem.
  • Develop test plans, test benches and tests, creating sequencers, drivers, checkers, and monitors in a UVM environment.
  • Apply formal methods to supplement stimulus based verification.
  • Create and support test environments for different design hierarchy levels.
  • Support unit and super-unit debug on simulation and emulation platforms.
  • Technically direct and mentor the GPU memory system verification team.
Experience Requirements:
  • Experienced Samsung with verification methodology such UVM/VMM/OVM. UVM is preferred.
  • Successfully verified a significant component of a memory hierarchy, e.g. a level2 cache unit.
  • Developed test plans of complex systems containing multiple state machines and protocol rules.
  • Composed functional coverage assertions, preferably using system Verilog.
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