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RTL Design Engineer (ASIC/FPGA)

Location: San Jose, CA
Job # 10106099
Date Posted : 11-01-2017
We have following urgent need with our client

Title -  RTL Design Engineer (ASIC/FPGA any one)
Duration - Full Time
Location - San Jose-CA
Rate : DOE

Required Skills
  • RTL Design Engineer with WI-FI domain.
  • Solid understanding of fundamentals of wireless communication physical and MAC layer concepts is required.
  • 802.11 protocol is preferred.
  • Communication techniques (PHY, FFT, Filters, modulations, coding, acquisition)
  • Wireless or wireline modem communications or DSP background.
  • General knowledge in design process, digital design, design (hw/sw) verification tools and techniques, communications systems, computer architecture, etc.
  • Familiarity with Verilog/SV or VHDL
  • Knowledge of Scripting and automation skills: Unix/Linux shell programming, Perl, Java, Makefile, XML.
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